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    Dynamic Engineering Corporation - www.dyenco.com

    Firmware Design

    We define ‘firmware’ as any programmable design that is implemented at the time of manufacture, is held in some non-volatile device and is not generally changed or managed by the end user. So firmware is typically ‘firm’ in the sense that it resides in hardware and controls the behavior of hardware – either microcontrollers or FPGAs.

    Microcontrollers

    Microcontrollers (MCUs), are microprocessors with integral peripherals – such as Serial Interfaces, Timers/Counters, PWM (Pulse-Width Modulation), ADCs (Analog-to-Digital Converter), DACs (Digital-to-Analog Converters) – to name just a few.

    We survey the offerings across multiple vendors and families to identify the device (or devices) that most closely match the design requirements during the Hardware Design phase. We take into account such parameters as: Data Bus Width, Architecture (CISC/RISC/DSP), Speed, Number of Inputs & Outputs, Interface Requirements, Cost, Power Consumption, Physical Packaging and so on.

    Often, modern microcontrollers allow for the reassignment of pins – either for general purpose digital IO (Input/Output) or peripheral functions. This process is coordinated with the hardware design process, along with the selection of required peripherals in concert with the System Architecture. Once the peripherals are selected and the pins are assigned, we design the architecture of the code itself – partitioning functional and logical blocks into modules, classes and methods (or functions). Finally, we proceed with the detailed firmware design, implementation and test.

    We select the appropriate tool-chain for the selected device(s) as well as the language (typically “C” and “C++” with some assembly as required). We employ a revision control system (Subversion) on all source and configuration files.

    FPGAs and other Programmable Logic

    Unlike the code that must run in a serial, sequential manner in MCUs, FPGAs (Field-Programmble Gate Arrays) employ massive parallel processing using a programmable sea of logic. This has architectural implications for how a particular problem is solved. FPGAs (PLDs/CPLDs) are much better suited to processing data quickly in a clock-synchronous, pipe-lined manner and therefore lend themselves to Digital Signal Processing (DSP).

    We select the physical FPGA based on the physical requirements such as block memory, speed, signalling levels, number of inputs and outputs and of course, cost. We also determine if we need to include additional Hard IP (Intellectual Property) such as High-Speed Serial Transceivers (to support PCI Express and so on), Microcontroller Cores (for example – PowerPC or ARM). We may also incorporate some Third Party IP to augment the process – for example DMA (Direct-Memory Access) capability.

    Once we select the specific FPGA (or FPGAs) for a given design, we design the architecture of the internal logic. As an FPGA is actually implemented in true hardware, the block partitioning reflects the physical processing steps (flow of data) in a block-diagrammatic and hierarchical manner. We identify the function and signalling standard for each pin in concert with the hardware design step and will an eye toward potential modification during the PCB layout step. Once we have the design partitioned into various blocks and modules, we proceed with the actual implementation using an HDL (Hardware Desciption Language) such as VHDL or Verilog.

    As with MCU Firmware, we select the appropriate tool-chain for the selected device(s) as well as the language (typically VHDL). We employ a revision control system (Subversion) on all source and configuration files.

    Documentation

    Though the goal is tested hardware, what we really deliver is design files and documentation. As such, we author a number of documents specifically tailored to the specific design and client. For firmware this typically includes Requirements, Theory of Operation, Block Diagrams, Timing Diagrams, Address (Register) Maps, User Manuals and so on. We comment our code to coincide with the supporting documents and allow an engineer skilled in the art to maintain the design as required.


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